The present invention relates to a technology which is effective when applied to a cell peripheral layout technique or a breakdown voltage enhancement technique in a semiconductor device (or a semiconductor integrated circuit device).
Japanese Unexamined Patent Publication No. 2007-116190 (Patent Document 1) or US Patent Publication No. 2005-098826 (Patent Document 2) corresponding thereto discloses various structures in regard to peripheral layout around a cell region in a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a Super-Junction structure manufactured by a Multi-Epitaxial method or a Trench insulating film filling method (in-trench ion implantation method). Examples of the structures include a P− Resurf region, a ring-like peripheral P-type drift region formed by an in-trench ion implantation, a vertically arranged linear peripheral P-type drift region and a divided and vertically/parallely arranged linear peripheral P-type drift region each formed by a trench insulating film filling method, and the like.
Japanese Unexamined Patent Publication No. Sho 59 (1984)-76466 (Patent Document 3) or U.S. Pat. No. 4,691,224 (Patent Document 4) corresponding thereto discloses a technique which arranges a plurality of Field Limiting Rings around a main junction in a silicon-based Planar semiconductor device and provides a Field Plate in the form of an insulating film coupled to the field limiting rings and inwardly extending toward the main junction of an active region, thereby improving a breakdown voltage.
Japanese Unexamined Patent Publication No. Hei 6 (1994)-97469 (Patent Document 5) or U.S. Pat. No. 5,804,868 (Patent Document 6) corresponding thereto discloses a technique which places field plates brought into a floating state, i.e., Floating Field Plates over, e.g., an insulating film around boundary regions between the main junction of an active region and field limiting rings in an IGBT (Insulated Gate Bipolar Transistor) so as to prevent the IGBT from being affected by external charge.
A paper written by Trajkovic and three others (Non-Patent Document 1) discloses a technique which provides the both ends of each of P+-type field limiting rings with a shallow low-concentration P-type region (on the active region side) and a shallow low-concentration N-type region (on the chip-edge side) in a Termination area of a power MOSFET (Power Metal Oxide Semiconductor Field Effect Transistor), thereby preventing a reduction in breakdown voltage due to external charge.